Verilog 50 Mhz 1hz | Clock Divider

// Generate 50 MHz clock (period = 20 ns) initial begin clk_50mhz = 0; forever #10 clk_50mhz = ~clk_50mhz; // 10ns half period = 20ns full period end

localparam COUNTER_MAX = 25_000_000 - 1; // 24,999,999 reg [24:0] counter; // 25 bits needed (2^25 = 33,554,432 > 25M) clock divider verilog 50 mhz 1hz

// Stage 1: 50 MHz → 100 Hz (divide by 500,000) clock_divider #(50_000_000, 100) stage1 (clk_50mhz, rst_n, clk_100hz); // Generate 50 MHz clock (period = 20

// Test sequence initial begin $dumpfile("dump.vcd"); $dumpvars(0, tb_clock_divider); // Initialize rst_n = 0; #100; // Release reset rst_n = 1; // Run for 2 seconds (simulation time) #2_000_000_000; // 2 seconds of simulation $finish; end forever #10 clk_50mhz = ~clk_50mhz

// Instantiate the clock divider clock_divider_50M_to_1Hz uut ( .clk_50mhz(clk_50mhz), .rst_n(rst_n), .clk_1hz(clk_1hz) );