wire [3:0] wgray = wptr ^ (wptr >> 1); wire [3:0] rgray = rptr ^ (rptr >> 1);
always @(posedge clk_dst or negedge rst_n) begin if (!rst_n) sync, meta <= 2'b00; else sync, meta <= meta, sig_src; end
always @(posedge HCLK or negedge HRESETn) begin if (!HRESETn) HREADYOUT <= 1'b1; else begin if (HREADY && HTRANS == NONSEQ) begin if (HWRITE) memory[HADDR[11:2]] <= HWDATA; else HRDATA <= memory[HADDR[11:2]]; HREADYOUT <= 1'b1; end else HREADYOUT <= 1'b1; // wait-state insertion possible end end endmodule
assign sig_dst = sync; endmodule module async_fifo #(DEPTH=8, WIDTH=16) ( input wclk, rclk, wrst_n, rrst_n, input wr_en, rd_en, input [WIDTH-1:0] wdata, output [WIDTH-1:0] rdata, output full, empty ); reg [WIDTH-1:0] mem [0:DEPTH-1]; reg [$clog2(DEPTH):0] wptr, rptr; // Gray coded
// ALU inside execute wire [31:0] alu_out = (opcode == ADD) ? ID_EX_rs1 + ID_EX_rs2 : ...;